Reversible computing with mechanical links and pivots

With the concern that “Moore’s Law is dead,” new interest has grown for unconventional forms of computing. This includes:

• quantum computing (for atomic simulations and specific NP approximation algorithms)
• analog computing (for fast-and-efficient-but-error-prone computation, such as neural net inference)
• reversible computing (for maximum energy efficiency)

It is believed that the most efficient computing devices would use little or no entropy during reversible computations, and only consume energy during non-reversible parts of computation. Specifically, the Landauer’s principle states that all non-physically-reversible computation operations consume at least \(2.9 \times 10^{21}\) J of energy at room temperature (and less as the temperature drops).

Are we at the theoretical maximum efficiency yet? No. Using some back-of-the-napkin math:

• AMD Ryzen Threadripper 7995WX has about 12 TFLOPS of FP32 (single-precision) compute (link)
• Assuming 30 irreversible computations per FP32 operation (from Claude), we have 10^14.5 irreversible computations per second
• At 350 W this is about \(10^{-12}\) J per irreversible computation, or about 9 orders of magnitude less efficient than the theoretical maximum

Even if a CPU like the AMD Ryzen Z1 Extreme or Apple M4 can improve this efficiency by a factor of 10 (which is too generous), we’re still a long way out from hitting the theoretical wall.

Nevertheless, it is both fun and prudent to imagine how different paradigms of computing would work. These different paradigms might even be competitive in certain niches long before transistors hit a wall. My favorite reversible computing scheme comes from a paper named Mechanical Computing Systems Using Only Links and Rotary Joint. In it, they use links and rotary joints (hinges) to build Turing-complete computing machines.

The most basic element is a “lock.” It’s constructed with two triangles that are allowed to slide back and forth. However, once the top triangle has been pushed forward, it prevents the bottom triangle from being pushed forward (and vice versa). It’s called a “lock” because the first triangle to get pushed forward will “lock out” the other.

The demo below is made from springs and pivot points. Drag the sliders to engage the top and bottom parts of a lock.

Top Input:

Bottom Input:

In principle, these locks could be constructed out of physical materials on very small scales. The authors of the original paper provided this example schematic of a 30 x 30 x 7 nm lock constructed out of carbon:

Ultimately, our binary convention will be that either the “1” line or the “0” line of a bit will always be engaged. A balance helps make this happen. It consists of two locks and a lever before them. On the forward edge of a clock, it forces a horizontal translation through whichever lock is not already engaged.

Try engaging only one of the two locks (top or bottom) and then engaging the clock. The clock will “flow through” whichever lock has not already been engaged by the inputs:

Top Input:

Bottom Input:

Clock Input:

The last thing that we will need to construct a NAND gate is a way to route and split signals. It turns out to be relatively simple:

Input:

And now we are ready to construct a NAND gate, which is a “universal gate” (i.e., you can implement any truth table using only NAND gates). We first use two “wires” for each input. If A is TRUE, then the first wire is pushed forward. If A is FALSE, then the second wire is pushed forward. Likewise, if B is TRUE then the third wire is pushed forward, and the fourth wire is pushed forward if B is FALSE.

We expect to always have exactly two of these wires push forward for any computation. Following these input wires, we see that each individual wire engages exactly two locks, preventing the thrust of the clock from flowing through that pathway. Since there are four pathways, we must make sure that only one pathway is unlocked at any time. Then, when the clock arrives, that pathway will receive the forward thrust.